VHDL Parser   We partner with Verific to deliver the most robust VHDL parser on the market.   Fastest VHDL reader available: Parses, analyses and elaborates 10,000 lines/second RTL, 30,000 lines/second flat-netlist code. (Average throughput, 2 Ghz Xeon, Red Hat Linux 8.0).   VHDL 93 as well as VHDL 87 support.   RTL synthesis subset semantic checking.   FSM and RAM extraction/recognition from RTL.   100% language coverage supported for analysis.   Wide language subset supported for elaboration, including IEEE 1164, unrestricted multiple libraries, records, multi-dimensional arrays, arrays of anything, generics, configurations, user-defined and overloaded functions/procedures/enumeration types, variable-indexing etc.