SNAP
Timing GUI
(Histogram,Path Reports,
Path Traversal
etc.)
Overview
This package is
based on our delay analysis package and produces typical path
delay reports along path delay
statistics, constraint violation reports etc. The correctness
of results in the "basic" mode has been verified by
multiple
customers against the industry standard tool. This can be further
customized to handle special requirements which
may be required by special technology or special design styles/architecture
that you might be deploying, for example,
timing analysis for asynchronous blocks or mixed synchronous/asynchronous
blocks. Intuitive
Timing GUI allows
for path highlighting and traversal.
For more details
on features, please check out the individual components used in
this package:
Timing
Engine
Asynchronous Timing Engine
Delay Engine
Verilog Parser/Elaborator
(Netlist) or Physical Data
(DEF) Elaborator
Library Elaborator
ALF Parser or Library
Parser
Command Parser/Interpreter
Message/Error/Help Mechanism
Variable Mechanism
Design Database
Inputs
Library Format,
ALF, LEF, SPEF, DEF, Verilog, SDF, timing constraints, clock definitions
Outputs
Path reports,
Constraint violation reports, path delay histograms.
Uses/Flows
Typical timing analysis with customized delay engine
and customized timing engine.
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