Overview

This is a gate-level synthesis package which translates and maps synthesizable verilog and VHDL RTL files onto a specified
technology library. There are two distinct stages to this tool, RTL compilation and Synthesis/Technology-Mapping. You can either
buy the entire RTL to mapped-netlist package or can utilize your own tool for RTL compilation and use our tool only for
synthesis/optimization. Some features of this tool are:

Accepts standard contraint files.
Selective synthesis mechanism allows one to synthesize or resynthesize only a targetted section of the design.
Physical data is integrated and one can read in placed designs (with extracted parasitics information).
Integrated with incremental placement/timing, provides a true user-driven physical synthesis system.

For more details on features, please check out the individual components used in this package:

Verilog Parser or VHDL Parser or DEF Parser
RTL Elaborator
LIB parser or ALF Parser
LEF Parser
SDF Parser
SPEF Parser
Synthesis
Timing Engine
Delay Engine
Command Parser/Interpreter
Message/Error/Help Mechanism
Variable Mechanism
Design Database


Inputs

Verilog, VHDL, LIB, ALF, LEF, SPEF, DEF, Timing constraints and clock definitions.

Outputs

Verilog, DEF (if placed originally or purchased with placement package). 

Uses/Flows