Synthesis (SNAP-06)    Currently we provide a basic quick synthesis tool with the goal being to get initial synthesized netlist as quickly into layout at possible.         Area-driven and timing-driven logic synthesis.   Algorithms can be customized for libraries with specialized gates, structured ASIC, FPGAs etc.   Numerous user controls allows trade-offs between run-time and quality of results.   Smart synthesis controls in conjunction with our static timing analysis speeds up constraint-driven synthesis and improves quality of results. - Automatic hierarchical synthesis.   User controlled hierarchy manipulations to improve runtime/QOR.   Handles pre-mapped logic and don't touch attributes.       Future           Improved sequential element mapping.