Overview

One can deploy our simulation package in a timed simulation mode or in cycle-based simulation mode. The timed 
simulation mode is based on our delay analysis engine and performs simulation based on actual delays calculated. 
Cycle based gate-level simulation is purely functional simulation to assert correctness of signal values. One can customize this 
package to take into account special technology, design style, or architecture. One can also customize this package 
to produce variety of reports. For example, one may deploy this package to calculate exact cross-talk based on actual 
transitions, or make sure that timing window assumptions made for cross-talk analysis were realistic, or to derive 
cross-talk vulnerability, or to derive power dissipation numbers based on signal switching, etc. 

For more details on features, please check out the individual components used in this package:

Gate-level Simulation Engine
Timed Simulation Engine
Timing Engine
Asynchronous Timing Engine
Delay Engine
Verilog Parser/Elaborator (Netlist)  or Physical Data  (DEF) Elaborator
Library Elaborator
ALF Parser or Library Parser
Command Parser/Interpreter
Message/Error/Help Mechanism
Variable Mechanism
Design Database

Inputs

Library Format, ALF, LEF, SPEF, DEF, Verilog, SDF, VCD, Signal values or signal transition inputs, Signal values or 
signal transition constraints.

Outputs

VCD, Waveform diagrams

Uses/Flows

Functional Simulation:

Timed Simulation: