The main purpose of this package is to achieve design closure based on more accurate physical data by deployment 
of variety of post-placement and post-route techniques. The closure may be in the form of timing, area, power, 
placement/routing (for example, congestion removal). We are not revealing any more information on this package at 
this time. Please contact us if you are interested in this product. 

For more details on features, please check out the individual components used in this package:

Physical Optimization
Timing Engine
Asynchronous Timing Engine
Delay Engine
Placement
Resynthesis
Verilog Parser/Elaborator (Netlist)  or Physical Data  (DEF) Elaborator
Library Elaborator
ALF Parser or Library Parser
Command Parser/Interpreter
Message/Error/Help Mechanism
Variable Mechanism
Design Database



Inputs

Library Format, ALF, LEF, SPEF, DEF, Verilog, SDF

Outputs

DEF, Verilog, ECO files, 

Uses/Flows

Please contact us for more information.