Verilog Parser RTL

	Verilog Parser (RTL) (SNAP-02)

	Standard verilog parser and AST constructor. AST data structure are stored internally for future elaboration or cross-referencing with gate-level/physical database. Features Current

		Efficient AST structure based internal storage.
		AST traversal capability.

	Future

		Verilog file line number cross-referencing
		Binary read/write from the database