Verilog Parser/Elaborator (Netlist) (SNAP-01)   This is a standard verilog gate-level netlist parser. It can read multiple verilog files (possibly hierarchical) and populate the design database with all cross-references resolved.  Features         Conforming to IEEE standard 1364 (only for the gate-level  netlist part)   Supports constants, port to port assigns, buses, and hierarchical modules.   Allows black-boxes (i.e. reference cell not available in library).   Macro expansions/substitutions and include files will be added in the future.